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스터디/Nand 2 Tetris



1. Nand2Tetris

1.1. 9/26()


  • : , , .

  • 향 :
    • : 3 + a(?)
      • : max 5 .
  • : ? // 1
  • : zp
  • : nand2Teris
  • : ppt .
  • :
    • ->.
    • 환 -> + 흥 ? .
    • -> 해.

  • : chapter 0,1 .

1.2. 9/29()


1.2.1.


  • Chapter1
  • 함.
  • Nand gate primitive gate , 트 Not, And, Or, Xor, Mux, Demux Nand .
  • Mux Demux , , Mux Mux . , 4way Mux 2Way Mux 3 .
  • HDL Code

  • Not Gate


CHIP Not2 {

    IN  a;
    OUT out;

	PARTS:
	Nand(a = a, b = a, out = out);
}


  • And Gate


CHIP And {

    IN  a, b;
    OUT out;
	PARTS:

	Nand(a = a, b = b, out = x);
	Nand(a = x, b = x, out = out);
}


  • Or Gate


CHIP Or {

    IN  a, b;
    OUT out;

	PARTS:
	Nand(a = a, b = a, out = x1);
	Nand(a = b, b = b, out = x2);
	Nand(a = x1, b = x2, out = out);
}


  • Xor Gate


CHIP Xor {

    IN  a, b;
    OUT out;

	PARTS:
	Nand(a = a, b = a, out = nota);
	Nand(a = b, b = b, out = notb);
	Nand(a = nota, b = b, out = x1);
	Nand(a = a, b = notb, out = x2);
	Nand(a = x1, b = x2, out = out);
}


  • Mux


CHIP Mux {

    IN  a, b, s;
    OUT out;

	PARTS:
	Nand(a = s, b = s, out = nots);
	Nand(a = a, b = s, out = x1);
	Nand(a = b, b = nots, out = x2);
	Nand(a = x1, b = x2, out = out);
}


  • Mux 4way


CHIP Mux4way {

    IN  a[4], s[2];
    OUT out;

	PARTS:
	Nand(a = s[0], b = s[0], out = nots0);
	Nand(a = s[1], b = s[1], out = nots1);
	
	Nand(a = a[0], b = s[1], out = x0);
	Nand(a = a[1], b = nots1, out = x1);
	
	Nand(a = a[2], b = s[1], out = x2);
	Nand(a = a[3], b = nots1, out = x3);
	
	Nand(a = x0, b = x1, out = xx0);
	Nand(a = x2, b = x3, out = xx1);
	
	Nand(a = xx0, b = s[0], out = xxx0);
	Nand(a = xx1, b = nots0, out = xxx1);
	
	Nand(a = xxx0, b = xxx1, out = out);
}


  • Demux
    Demux Mux 4way Demux 파 ㅡㅡ;

1.2.2.


  • Chapter2 .

1.2.3.


  • , 행합. 학 행해, . . , Nand gate . , ppt . 한 4way MUX , .. . -
  • . , . nand nand . -
  • 행했... ...하 . ... . -

1.3. 10/6()


1.3.1.


  • half-adder, full-adder, 16bit-adder, incremental adder, ALU .

  • Half-Adder


CHIP HalfAdder {
    IN a, b;    // 1-bit inputs
    OUT sum,    // Right bit of a + b 
        carry;  // Left bit of a + b

    PARTS:
	And(a = a, b = b, out = carry);
	Xor(a = a, b = b, out = sum);	
    
}

  • Full-Adder


CHIP FullAdder{
    IN a, b, c;  // 1-bit inputs
    OUT sum,     // Right bit of a + b + c
        carry;   // Left bit of a + b + c
    PARTS:
    // Put you code here:
	Xor(a=a, b=b, out=s1);
	And(a=a, b=b, out=c1);
	Xor(a=s1, b=c, out=sum);
	And(a=s1, b=c, out=c2);
	Or(a=c1, b=c2, out=carry);
}


  • 16bit Adder


CHIP Add16 {
    IN a[16], b[16];
    OUT out[16];
	
	PARTS:
	FullAdder(a = a[0], b = b[0], c = false, sum = out[0], carry = c1);
	FullAdder(a = a[1], b = b[1], c = c1, sum = out[1], carry = c2);
	FullAdder(a = a[2], b = b[2], c = c2, sum = out[2], carry = c3);
	FullAdder(a = a[3], b = b[3], c = c3, sum = out[3], carry = c4);
	FullAdder(a = a[4], b = b[4], c = c4, sum = out[4], carry = c5);
	FullAdder(a = a[5], b = b[5], c = c5, sum = out[5], carry = c6);
	FullAdder(a = a[6], b = b[6], c = c6, sum = out[6], carry = c7);
	FullAdder(a = a[7], b = b[7], c = c7, sum = out[7], carry = c8);
	FullAdder(a = a[8], b = b[8], c = c8, sum = out[8], carry = c9);
	FullAdder(a = a[9], b = b[9], c = c9, sum = out[9], carry = c10);
	FullAdder(a = a[10], b = b[10], c = c10, sum = out[10], carry = c11);
	FullAdder(a = a[11], b = b[11], c = c11, sum = out[11], carry = c12);
	FullAdder(a = a[12], b = b[12], c = c12, sum = out[12], carry = c13);
	FullAdder(a = a[13], b = b[13], c = c13, sum = out[13], carry = c14);
	FullAdder(a = a[14], b = b[14], c = c14, sum = out[14], carry = c15);
	FullAdder(a = a[15], b = b[15], c = c15, sum = out[15], carry = c16);


}


  • Incremental




CHIP Inc16 {
    IN a[16];
    OUT out[16];

    PARTS:
	
	FullAdder(a = a[0], b = false, c = true, sum = out[0], carry = c1);
	FullAdder(a = a[1], b = false, c = c1, sum = out[1], carry = c2);
	FullAdder(a = a[2], b = false, c = c2, sum = out[2], carry = c3);
	FullAdder(a = a[3], b = false, c = c3, sum = out[3], carry = c4);
	FullAdder(a = a[4], b = false, c = c4, sum = out[4], carry = c5);
	FullAdder(a = a[5], b = false, c = c5, sum = out[5], carry = c6);
	FullAdder(a = a[6], b = false, c = c6, sum = out[6], carry = c7);
	FullAdder(a = a[7], b = false, c = c7, sum = out[7], carry = c8);
	FullAdder(a = a[8], b = false, c = c8, sum = out[8], carry = c9);
	FullAdder(a = a[9], b = false, c = c9, sum = out[9], carry = c10);
	FullAdder(a = a[10], b = false, c = c10, sum = out[10], carry = c11);
	FullAdder(a = a[11], b = false, c = c11, sum = out[11], carry = c12);
	FullAdder(a = a[12], b = false, c = c12, sum = out[12], carry = c13);
	FullAdder(a = a[13], b = false, c = c13, sum = out[13], carry = c14);
	FullAdder(a = a[14], b = false, c = c14, sum = out[14], carry = c15);
	FullAdder(a = a[15], b = false, c = c15, sum = out[15], carry = c16);
}


  • ALU




1.3.2.

  • chapter 3 .

1.3.3.

  • CPU .. ㅋㅋ -
  • ALU . ( ) . -
  • . -

1.4. 11/3()


1.4.1.

  • Chapter 4
  • Hack Machine language .
    D - data, A - address, M - memory
    e.g. A - 32, M M32. M , A memory address
    2 Instruction . Instruction 2Byte.
  • A-Instruction : @value // Where value is either a non-negative decimal number or a symbol referring to such number.
    Binary : 0vvv vvvv vvvv vvvv
  • C-Instruction : dest=comp;jump // Either the dest or jump fields may be empty.
    // If dest is empty, the "=" is omitted;
    // if jump is empty, the ";" is omitted;

  • { comp }{dest }{jump}
    Binary : 111a c1c2c3c4 c5c6d1d2 d3j1j2j3

  • A-instruction , value A .
    A M , , D 함.

  • Chapter4
  • PPT

1.4.2.



  • 1 ~ 100 ()
     0	@100
    1	M=1
    2	@150
    3	M=0
    4	@100
    5	D=M
    6	@100
    7	D=D-A
    8	@18
    9	D;JGT
    10	@100
    11	D=M
    12	@150
    13	M=D+M
    14	@100
    15	M=M+1
    16	@4
    17	0;JMP
    18	@18
    19	0;JMP
     
     
  • ()
    //Memory[10] = A
    //Memory[11] = B
    //Memory[12] = Dest
    
    0	@20
    1	D=A
    2	@10
    3	M=D
    4	@20
    5	D=A
    6	@11
    7	M=D
    8	@12
    9	M=0
    10	@11
    11	D=M
    12	@22
    13	D;JEQ
    14	@10
    15	D=M
    16	@12
    17	M=D+M
    18	@11
    19	M=M-1
    20	@10
    21	0;JMP
    22	@22
    23	0;JMP
    
     
  • (환)
img.png
[PNG image (303.11 KB)]


  • I/O Handling, ()(BLACK , WHITE )
    
    0	@24576
    1	D=M
    2	@0
    3	D;JEQ
    4	@66
    5	D=D-A
    6	@1000
    7	D;JEQ
    8	@24576
    9	D=M
    10	@87
    11	D=D-A
    12	@2000
    13	D;JEQ
    14	@0
    15	0;JMP
    
    1000	@24576
    1001	D=M
    1002	@1000
    1003	D;JEQ
    1004	@76
    1005	D=D-A
    1006	@0
    1007	D;JNE
    1008	@24576
    1009	D=M
    1010	@1008
    1011	D;JEQ
    1012	@65
    1013	D=D-A
    1014	@0
    1015	D;JNE
    1016	@24576
    1017	D=M
    1018	@1016
    1019	D;JEQ
    1020	@67
    1021	D=D-A
    1022	@0
    1023	D;JNE
    1024	@24576
    1025	D=M
    1026	@1024
    1027	D;JEQ
    1028	@75
    1029	D=D-A
    1030	@0
    1031	D;JNE
    1032	@24555
    1033	M=-1
    1034	@0
    1035	0;JMP
    
    2000	@24576
    2001	D=M
    2002	@2000
    2003	D;JEQ
    2004	@72
    2005	D=D-A
    2006	@0
    2007	D;JNE
    2008	@24576
    2009	D=M
    2010	@2008
    2011	D;JEQ
    2012	@73
    2013	D=D-A
    2014	@0
    2015	D;JNE
    2016	@24576
    2017	D=M
    2018	@2016
    2019	D;JEQ
    2020	@84
    2021	D=D-A
    2022	@0
    2023	D;JNE
    2024	@24576
    2025	D=M
    2026	@2024
    2027	D;JEQ
    2028	@69
    2029	D=D-A
    2030	@0
    2031	D;JNE
    2032	@24555
    2033	M=0
    2034	@0
    2035	0;JMP
    
     
  • I/O Handling, (환)(BLACK , WHITE )

sample.png
[PNG image (300.59 KB)]




1.4.3.


  • MIPS 행했, MIPS . Symbol ( Cpu emulator ), 2~3 . I/O Handling , . "High-Level Language ?" . , . 1/3 행했, 12 1/2 행할 . 행해 . -

1.4.4.


  • Chapter 5 .

1.5. 11/17()


1.5.1.


  • Von Neumann machine (circa 1940)

    Memory (data + instruction) + CPU(ALU + Registers + Control) + Input device & Output device


    (Nand ) , Combinational Chip Sequential Chip . Computer Architecture .


  • The Hack Computer

    A 16-bit Von Neumann platform
    The instruction memory and the data memory are physically separate
    Screen: 512 rows by 256 columns, black and white
    Keyboard: standard

  • Instruction memory(ROM)

    ROM .
    ROM 16bit .

    instruction = ROM32Kaddress

  • Memory(RAM)
    Data memory


    k = address
    out = RAMk


  • k = address
    x = in
    load = 1
    RAMk = x

    Screen(memory map)

    Screen 한 RAM . Screen . CPU Screen

    Keyboard(memory map)
    Keyboard 한 RAM . Keyboard . CPU key .

  • CPU
  • Computer ( logic )

    architecture .

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